Chinese chipmakers burn through wafers to match EUV density
SMIC and CXMT use multiple DUV exposures to bypass ASML restrictions, resulting in lower yields and higher costs per die.
By Ivan Dvorak ·
Morgan Stanley estimates that Chinese DRAM manufacturer CXMT produces only about one-third as many bits per wafer as its Western competitors. This efficiency gap stems from the need to use older deep ultraviolet lithography equipment because export controls have blocked access to ASML's extreme ultraviolet machines. The workaround requires exposing critical chip layers multiple times, a process that increases defects and production time.
Chris Mack, co-founder and CTO of Fractilia, explained that industry standards previously held that three exposures on a 193 immersion tool cost about the same as one EUV exposure. However, once manufacturers require four masks, EUV becomes the cheaper option. Each additional pattern must align precisely with previous etchings, creating accumulated overlay errors. Designers often add space around features to compensate, which enlarges the chip and reduces the number of dies per wafer.
"You don't sell wafers, you sell die," Mack said. This distinction is critical because wafers cost tens of thousands of dollars each. The Kirin 9030 processor, analyzed recently, indicates that SMIC has moved its DUV-based process closer to 5nm density. However, it still trails the leading processes from TSMC and Samsung. A 2023 teardown of the Huawei Mate 60 Pro showed SMIC used a second-generation 7nm-class process without EUV.
Memory development presents specific challenges. Morgan Stanley described lithography access as a hard ceiling for Chinese memory development. While Micron developed its 1-alpha DRAM without EUV, it eventually turned to EUV for its 1-gamma DRAM. The newer generation delivers more than 30% greater bit density per wafer than the previous 1-beta generation. Mack noted that he would be hard pressed to believe a 3nm or 2nm node could be economically viable without EUV.
DUV technology still offers potential for progress. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade. Mack added that China could make significant strides if it utilized the full 193 immersion ecosystem and designed products around it, though he emphasized that memory is much easier to produce this way than logic chips.
Morgan Stanley projects that CXMT will lift its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank assumes CXMT stays on 1-alpha technology without EUV during this period. The firm also expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030. Despite this growth, gaps in EUV, high-bandwidth memory, and advanced software are expected to persist.
Manufacturers can continue pushing DUV limits by accepting larger dies, poorer yields, or longer manufacturing times. They can also add production capacity to offset efficiency losses. The strategy allows Chinese foundries to maintain progress in cutting-edge silicon while managing the financial and technical trade-offs of avoiding the most advanced lithography tools available.
